december 2011 ? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 rv4141a ? low-power, ground-fault interrupter rv4141a low-power, ground-fault interrupter features ? powered from the ac line ? built-in rectifier ? direct interface to scr ? 500 a quiescent current ? precision sense amplifier ? adjustable time delay ? minimum external components ? meets ul 943 requirements ? compatible with 110v or 220v systems ? available in an 8-pin soic package description the rv4141a is a low-power controller for ac- receptacle, ground-fault circ uit interrupters. these devices detect hazardous cu rrent paths to ground and ground to neutral faults. the circuit interrupter then disconnects the load from t he line before a harmful or lethal shock occurs. internally, the rv4141a contai ns a diode rectifier, shunt regulator, precision sense amp lifier, current reference, time-delay circuit, and scr driver. two sense transformers, scr, solenoid, three resistors, and four capacitors complete the design of the basic circuit interrupter. the simple layout and minimum component count ensure eas e of application and long- term reliability. features not found in other gfci controllers include a low offs et voltage sense amplifier, eliminating the need for a coupling capacitor between the sense transformer and sense amplifier, and an internal rectifier to elim inate high-voltage rectifying diodes. the rv4141a is powered only during the positive half period of the line voltage, but can sense current faults independent of its phase relative to the line voltage. the gate of the scr is driven only during the positive half cycle of the line voltage. ordering information part number operating temperature range package packing method rv4141an -35 to +80c 8-lead, plastic dual-inline package (dip) rails rv4141amt -35 to +80c 8-lead, plastic small-ou tline integrated circuit (soic) tape and reel
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 2 rv4141a ? low-power, ground-fault interrupter block diagram figure 1. block diagram pin configuration figure 2. pin assignment pin definitions pin # name description 1 amp out sense amplifier output ? an external resistor to v fb sets the i fault threshold 2 v fb sense amplifier negative input 3 v ref sense amplifier positive input ? biased internally at +v s /2 4 gnd substrate ground for all circuitry 5 line anode of internal di ode connected to supply voltage 6 +v s supply input for rv4141a circuitry 7 scr trigger output for triggering ex ternal scr when a fault is detected 8 delay cap an external capacitor to ground sets the delay time for a ground fault to be present before triggering the scr
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 3 rv4141a ? low-power, ground-fault interrupter absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc power supply 10 ma p d internal power dissipation 500 mw t stg storage temperature range -65 +150 c t a operating temperat ure range -35 +80 c t j junction temperature +125 c t l lead soldering temperature 10 seconds, soic +260 c 60 seconds, dip +300 thermal characteristics symbol parameter typ. max. unit ? ja thermal resistance soic 240 c/w dip 160
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 4 rv4141a ? low-power, ground-fault interrupter electrical characteristics i line = 1.5ma and t a = +25c, r set = 650k ?? symbol parameter conditions min. typ. max. units shunt regulator (pins 5 to 4) v reg regulated voltage i 2-3 = 11a 25 27 29 v i line = 750a, i 2-3 = 9a 25 27 29 i q quiescent current v 5-4 = 24v 500 a sense amplifier (pins 2 to 3) v off offset voltage -200 0 200 v gbw gain bandwidth design value 3 mhz t sk slew rate design value 1 v/s i bias input bias current design value 30 100 na scr trigger (pins 7 to 4) r out output resistance v 7-4 = open, i 2-3 = a 3.8 4.7 5.6 k ? v out output voltage i 2-3 = 9 a 0 0.1 10.0 mv i 2-3 = 11 a 3.0 3.8 4.5 v i out output current v 7-4 = 0v , i 2-3 = 11 a 400 600 a reference voltage (pins 3 to 4) v ref reference voltage i line = 750a 12 13 14 v delay timer (pins 8 to 4) discharge / charge ratio i 2-3 = 0/11 a 1.8 2.5 3.0 a/a t dly delay time (1) c 8-4 = 12nf 2 ms i dly delay current i 2-3 = 11 a 30 40 50 a notes: 1. delay time is defined as starti ng when the instantaneous sense current (i 2-3 ) exceeds 6.5v/r set and ending when the scr trigger voltage v 7-6 goes high.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 5 rv4141a ? low-power, ground-fault interrupter circuit operation ( refer to figure 1 and figure 3. ) the precision op amp connec ted to pins 1 through 3 senses the fault current flow ing in the secondary of the sense transformer, converting it to a voltage at pin 1. the ratio of secondary curr ent to output voltage is directly proportional to feedback resistor, r set . r set converts the sense transformer secondary current to a voltage at pin 1. due to the virtual ground created at the sense amplifier input by its negative feedback loop, the sense transformer's burden is equal to the value of r in . from the transformer's point of view, the ideal value for r in is 0 ? . this causes it to operate as a true current transformer with minimal error. however, making r in equal to zero creates a lar ge offset voltage at pin 1 due to the sense amplifier's very high dc gain. r in should be selected as high as possible, consistent with preserving the transformer's operation as a true current mode transformer. a typical value for r in is between 200 and 1000 ? . as seen in equation (1), maximizing r in minimizes the dc offset error at the s ense amplifier output. the dc offset voltage at pin 1 contri butes directly to the trip current error. the offset voltage at pin 1 is: ) /( ec in set os rs r r v ? ? (1) where: v os = input offset voltage of sense amplifier; r set = feedback resistor; r in = input resistor; r sec = transformer secondary winding resistance. the sense amplifier has a specified maximum offset voltage of 200 v to minimize trip current errors. two comparators connected to the sense amplifier output are configured as a window detecto r, whose references are -6.5v and +6.5v, referred to pin 3. when the sense transformer secondary rms current exceeds 4.6/r set , the output of the wi ndow detector starts the delay circuit. if the secondary current exc eeds the predetermined trip current for longer than the delay time, a current pulse appears at pin 7, triggering the scr. the scr anode is directly connected to a solenoid or relay coil. the scr can be tripped only when its anode is more positive than its cathode. supply current requirements the rv4141a is powered direct ly from the line through a series-limiting resistor called r line ; its value is between 24k ? and 91k ?? the controller ic has a built-in diode ? rectifier, eliminating the need for external power diodes. ? the recommended value for r line ? is 24k ?? to 47k ? for ? 110v systems and 47k ??? to 91k ?? for 220v systems. when ? r line ? is 47k ??? the shunt regulator current is limited to ? 3.6ma. the recommended maximum peak line current ? through r line is 10ma. ? gfci application (refer to figure 3) the gfci detects a ground faul t by sensing a difference in current in the line and neutra l wires. the difference in current is assumed to be a fault current creating a potentially hazardous path from line to ground. since the line and neutral wires pass th rough the center of the sense transformer, only the diffe rential primary current is transferred to the secondary. assuming the turns ratio is 1:1000, the secondary current is 1/1000th the fault current. the rv4141a?s sense amplifier converts the secondary current to a voltage compared with either of the two window detector reference voltages. if the fault current exceeds the design va lue for the duration of the programmed time delay, the rv4141a sends a current pulse to the gate of the scr. detecting ground-to-neutral faults is more difficult. r b represents a normal ground fault resistance. r n is the wire resistance of the elec trical circuit between load/ neutral and earth ground. r g represents the ground-to- neutral fault condition. accord ing to ul 943, the gfci must trip when r n = 0.4 ? , r g = 1.6 ? , and the normal ground fault is 6ma. assuming the ground fault to be 5ma, 1ma, and 4ma goes through r g and r n , respectively, causing an effective 1ma fault current. th is current is detected by the sense transformer and am plified by the sense amplifier. the ground / neut ral and sense transformers are mutually coupled by r g , r n , and the neutral wire ground loop, producing a pos itive feedback loop around the sense amplifier. t he newly created feedback loop causes the sense amplifier to oscillate at a frequency determined by ground/neutral transformer secondary inductance and c4, which occurs at 8khz. c2 is used to program the ti me required for the fault to be present before the scr is triggered. refer to equation (2) for calculating the value of c2. its typical value is 12nf for a 2ms delay. r set is used to set the fault current at which the gf ci trips. when used with a 1:1000 sense transformer, its typical value is 1m ? for a gfci designed to trip at 5ma. r in should be the highest value possible that ensures a predictable secondary curr ent from the sense transformer. if r in is set too high, normal production variations in the transforme r permeability causes unit-to- unit variations in the secondary current. if it is too low, a large offset voltage error at pin 1 is present. this error voltage in turn creates a trip current error proportional to the input offset voltage of the sense amplifier. as an example, if r in is 500 ? , r set is 1m ? , r sec is 45 ?? and the v os of the sense amplifie r is its maximum of 200 v; the trip current error is 5.6%.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 6 rv4141a ? low-power, ground-fault interrupter the scr anode is directly connected to a solenoid or relay coil. it can be tripped only when its anode is more positive than its cathode. it must have a high dv/dt rating to ensure that line noise (generated by electrically noisy appliances) does not falsely trigger it. also the scr must have a gate driv e requirement less than 200 a. c3 is a noise filter that prevents high-frequency line pulses from triggering the scr. the relay solenoid should have a response time of 3ms or less to meet the ul 943 timing requirement. sense transformers and cores the sense and ground/neutral transformer cores are usually fabricated using high-permeability laminated steel rings. their single-turn primary is created by passing the line and neutral wire s through the center of its core. the secondary is usually from 200 to 1500 turns. transformers may be obtained from magnetic metals, inc. ( www.magmet.com ). calculating the values of r set and c2 determine the nominal ground-fault trip-current requirement. this is typically 5ma in north america (117v ac ) and 22ma in the uk and europe (220v ac ). determine the minimum delay time required to prevent nuisance tripping, typically 1 to 2ms. the value of c2 required to provide the desired delay time is: t c ? ? 6 2 (2) where: c2 is in nf and t is the desired delay time in ms. the value of r set to meet the nominal ground fault trip current specification is: 180(t/p) cos i n 4.6 r fault set ? ? ? (3) where: r set is in k ?? t is the time delay in ms; p is the period of the line frequency in ms; i fault is the desired ground fault trip current in ma rms; n is the number of sense transformer secondary turns. note: 2. this formula assumes an ideal sense transformer is used. the calculated value of r set may have to be changed up to 30% when using a non-ideal transformer. figure 3. gfi application circuit
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 7 rv4141a ? low-power, ground-fault interrupter physical dimensions c 7 typ 7 typ .430 max [10.92] b a .400 .373 [ 10.15 9.46 ] .250.005 [6.350.13] .036 [0.9 typ] .070 .045 [ 1.78 1.14 ] .100 [2.54] .300 [7.62] .060 max [1.52] .310.010 [7.870.25] .130.005 [3.30.13] .210 max [5.33] .140 .125 [ 3.55 3.17 ] .015 min [0.38] .021 .015 [ 0.53 0.37 ] .010 +.005 -.000 [ 0.254 +0.127 -0.000 ] pin #1 pin #1 (.032) [r0.813] (.092) [?2.337] top view option 1 top view option 2 .001[.025] c n08erevg c. does not include mold flash or protrusions. dambar protrusions shall not exceed d. does not include dambar protrusions. b. controling dimensions are in inches a. conforms to jedec registration ms-001, mold flash or protrusions shall not exceed variations ba e. dimensioning and tolerancing notes: reference dimensions are in millimeters .010 inches or 0.25mm. .010 inches or 0.25mm. per asme y14.5m-1994. figure 4. 8-lead, plastic dual-inline package (dip) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 8 rv4141a ? low-power, ground-fault interrupter physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 5. 8-lead, plastic small-outline integrated circuit (soic) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com rv4141a ? rev. 1.0.8 9 rv4141a ? low-power, ground-fault interrupter
|
